B. Read operations on RAM and ROM are not controlled by a clock.
C. SRAM and DRAM do not need power to maintain data.
D. The width of a word could vary
C
C
A
B
7. Choose the best answer below.
Is there a limit on the number of ways to express a Nand chip in terms of other chips?
No. Nand is made of two transistors and there are infinitely many ways to build transistors.
No. Nand is made of two transistors and there are infinitely many ways to build transistors.
Yes. Because Nands can only be built directly from transistors
Yes. Because there is a limited variety of other gates.
8. In the Hack machine there is an A register to hold the contents of the A-instruction but there is no equivalent register to hold the values of the C-instruction. Why not?
Because it is possible to wire up the hack CPU so that the wires holding the instruction can be routed directly to the chips controlling the CPU without the need for an intervening C-register.
The C register is not needed because we make use of the A-register to hold the C-instruction while decoding takes place.
The premise of the question is wrong - there is a C register in the hack machine.
The fact that instruction memory is ROM in the hack machine design means that a C register is not necessary. If the instruction memory were RAM then there would be a need to store the instruction in a C-register.
9. How does a programmer finish a program in Hack Assembler?
By specifying a label followed by an instruction that unconditionally jumps to itself.
By setting the address of the A register to zero.
By using a halt instruction
By including an instruction that is all zero bits at the end of the code and then jumping conditionally to that instruction.
10. Consider the DFF circuit in the leftmost part of figure 3.1 in textbook. This circuit is not, by itself suitable for storing a bit of information. Why is it not suitable?
Because there is no way to get a bit of information into the circut
Because the DFF always outputs its input from the previous clock cycle
Because after one clock cycle delay the dff reverts to zero
Because the DFF provides no way of synchronising the input and output signal
11. What is the capacity of the following memory in terms of bytes (B) or bits (b)?
128 KB
1 MB
256 Mb
131 Kb
12. Two DFFs are directly connected as shown in the following schematic. Consider the input signal 'in' in the following three clock cycles. What is the value of 'out' in clock cycle 3?
