SCD21 Processor Performance

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Clock Speed
The system clock generates a series of signals, switching between 0 and 1 several million times per second. The rate of switching is known as the "Clock Speed", and is measured in GHz (Gigahertz). Greater clock speed = Greater instruction execution/s
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Number of Cores
Each core is able to process a different instruction at the same time with its one FDE cycle, making the processor X times more powerful. However, it also uses X times as much power.
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Cache Memory
Cache is a small amount of expensive, high speed memory within the CPU. When an instruction is fetched from main memory, it is copeid into the cache so if it needs to be used again it can be done quickly.
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Pipelining (A-Level only)
The computer architecture allows the next instructions to be fetched at the same time as the processor is performing arithmetic and logic operations.
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Address Bus
When the processor wishes to read a word of data from memory, it puts the adress of the desired word on the address bus. THE WIDTH OF THE ADDRESS BUS DETERMINES THE MAXIMUM POSSIBLE MEMORY CAPACITY OF THE SYSTEM. 8 lines = 255 memory addresses.
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Data Bus
The data bus transmits the data held in a word of memory, between processor components and memory. The largest operand that can be held in a word is related to the size of the data bus. 16 lines = 2^16 - 1 max integer size.
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Other cards in this set

Card 2

Front

Each core is able to process a different instruction at the same time with its one FDE cycle, making the processor X times more powerful. However, it also uses X times as much power.

Back

Number of Cores

Card 3

Front

Cache is a small amount of expensive, high speed memory within the CPU. When an instruction is fetched from main memory, it is copeid into the cache so if it needs to be used again it can be done quickly.

Back

Preview of the back of card 3

Card 4

Front

The computer architecture allows the next instructions to be fetched at the same time as the processor is performing arithmetic and logic operations.

Back

Preview of the back of card 4

Card 5

Front

When the processor wishes to read a word of data from memory, it puts the adress of the desired word on the address bus. THE WIDTH OF THE ADDRESS BUS DETERMINES THE MAXIMUM POSSIBLE MEMORY CAPACITY OF THE SYSTEM. 8 lines = 255 memory addresses.

Back

Preview of the back of card 5
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