COM1031 - Computer Logic

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  • Created by: NiallJVS
  • Created on: 22-01-16 14:02
Propagation Delay
The finite time for a gate to respond to a change in the input signal(s).
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Combinational Logic
Combine logic gates, output depends solely on the input states.
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Sequential Logic
Use feedback from a sequence of circuits, output depends on input states and previous states.
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Half Adder
S = (A XOR B), C = (A AND B)
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Full Adder
S = ((A XOR B) XOR Ci), Co = (A AND B OR {(A XOR B) AND C})
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Latch
The state of the output is changed whenever the appropriate inputs change and the clock is asserted/1.
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Flip-Flop
The state of the output is changed whenever the appropriate inputs change and there is a clock edge/0.
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Address Bus
Specifies Memory Locations, uni-directional.
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Data Bus
Transfers data and instructions between the CPU and memory, bi-directional.
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Read/Write wire
Specifies either a read or write operation.
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Big-Endian
High byte stored first, low byte stored after.
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Little-Endian
Low byte stored first, high byte stored after.
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X, Y, Z Indirect Address
X - R26+R27; Y - R28+R29; Z - R30+R31
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Register range for direct addressing
R16-R31
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Difference between JMP and RJMP
RJMP adds and offset to, or subtracts from the program counter.
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BREQ
Branch if Equal (Zero Flag Set)
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BRNE
Branch if not Equal (Zero Flag Clear)
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BRCS
Branch if Carry Set
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BRCC
Branch if Carry Clear
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Stack Pointer
Contains the address of the (usually) top of the stack, so the stack (usually) grows downwards.
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PUSH
Push a value onto the stack
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POP
Pop a value off the stack
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Common Problems of a Stack
1. If you don't set the stack pointer, the default could be 0x0000 [R0], and pushing would overwrite R0. 2. Another PUSH writes to 0xFFFF [wraparound], where there is no SRAM. 3. Forgetting to POP/PUSH will cause RET to jump to incorrect address.
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CALL
Push the return address onto the stack. Jump to the called subroutine address.
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RET
Pops the saved return address from the stack. Jumps to that address.
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Interrupt
An interrupt is when an event requires immediate (or ASAP) action. This event is usually triggered by hardware, or by time.
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When an Interrupt Occurs...
1. The return address of the main program is saved onto the stack. 2. The Global Interrupt Enable I-bit is cleared. 3. The address of the appropriate interrupt vector is loaded into the PC. 3. This causes a JMP to the appropriate ISR.
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When the ISR is finished...
1. The Global Interrupt Enable I-bit is set. 2. The PC is loaded with the return address of the main program [from the stack]. 3. Execution of the main program resumes.
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Interrupt Service Routine
An ISR is the code that is executed when an interrupt occurs. Each interrupt has its own ISR and Interrupt Vector (the address of the ISR).
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Priority of Interrupts
Interrupt vectors lowest in memory have priority over those higher in memory.
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Examples of Interrupts
1. Timer1 Overflow Interrupt. 2. Timer1 Compare Match Interrupt 3. Input Capture Interrupt
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Difference between ROL and LSL
ROL sets the most far bit to the value of the carry flag. LSL sets the most far bit to 0.
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Similarity between ROL and LSL
Both multiply by 2.
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The Program Counter (PC)
A pointer to where the processor is up to in the execution of instructions. The memory address where the opcode is currently being executed and stored.
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The Memory Buffer Register (MBR)
Interfaces the data bus with several internal processor sub-units. When data is written to memory or when a read operation is perfored, the MBR acts as a temporary buffer.
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Microcontrollers
Typically contain RAM and ROM. Provide connections that may be used for control applications. May be regarded as a single chip computer that is programmed to perform a specific range of tasks.
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Maskable Interrupts
Interrupts of this type can be disabled. Such interrupts can be disabled when the processor is performing time critical operations.
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Non-Maskable Interrupts
Interrupts of this type cannot be disabled. These interrupts can occur at any time.
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Bus
A physical link comprising a group of connections which share a common purpose.
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Address Bus
For Memory Addresses
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Data Bus
To transfer data
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Control Bus
For timing
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Backplane Bus
One bus linking everything. Cost effective, but not as secure/reliable.
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Synchronous Bus
Transmitters and receivers are synchronised by clock. Used in high-speed transmission.
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Asynchronous Bus
Transmitters and receivers are not synchronised by clock. Used in low-speed transmission.
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Different Types of ROM
PROM (Programmable ROM), EPROM (Erasable Programmable ROM), Flash EPROM (i.e. memory stick).
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Different Types of RAM
DRAM (Dynamic RAM), SRAM (Static RAM), Non-Volatile RAM
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Cache Memory
A small amount of very fast/expensive memory located on/near to the processor. Spatial Locality - Holds instructions that are close to address of currently executed instruction. Temporal Locality - Recently executed instructions may soon be needed.
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Virtual Memory
Memory Management technique implemented using both hardware and software. Maps memory addresses used by a program [virtual addresses], into physical addresses in computer memory.
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Compilation
Carried out before program execution.
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Interpretation
Runs during program execution.
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Other cards in this set

Card 2

Front

Combine logic gates, output depends solely on the input states.

Back

Combinational Logic

Card 3

Front

Use feedback from a sequence of circuits, output depends on input states and previous states.

Back

Preview of the back of card 3

Card 4

Front

S = (A XOR B), C = (A AND B)

Back

Preview of the back of card 4

Card 5

Front

S = ((A XOR B) XOR Ci), Co = (A AND B OR {(A XOR B) AND C})

Back

Preview of the back of card 5
View more cards

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